Programmable logic devices, such as antifuses, are commonly used for changing the connectivity of an integrated circuit after fabrication. For example, one application of antifuses is in the repair of integrated circuit memory devices, such as random access memory (RAM) devices. Memory devices are often fabricated with several redundant elements (rows or columns) of memory cells that can be substituted for similar elements that are found to be defective. Antifuses can be selectively programmed to reroute the addresses of failing elements (rows or columns) such that functional redundant elements are addressed instead.
As fabricated in its unblown condition, the antifuse functions as a capacitor and presents a very high resistance, e.g., 10 Megaohms, between its terminals. The antifuse is programmed by shorting its terminals together, providing a relatively low resistance path of approximately between 200 ohms and 10 kiloohms. The programming is carried out by applying, across the terminals of the antifuse, a programming voltage of sufficient amplitude to cause breakdown of the dielectric interposed between its terminals.
Integrated circuit memory devices undergo extensive testing during manufacturing. Antifuses included in such memory devices are also tested prior to programming the antifuses. Antifuses are tested for failure mechanisms including defects in the dielectric between its terminals, defects in the contacts to the antifuse terminals, and other antifuse fault conditions. It is often desirable to provide an antifuse stress test, in which a voltage magnitude greater than an operating voltage, but less than a programming voltage is applied across the terminals of an antifuse to identify weak or defective antifuses, such as may result from dielectric defects, for example. The antifuse stress test is needed prior to actual programming of the antifuses. Since antifuse stress testing requires a different stress voltage than used during testing of the RAM memory cells, a separate testing operation is required to accomplish stress testing of antifuses.
Testing the RAM memory cells involves placing the integrated circuit memory device in a test mode, as distinguished from its normal operating mode, such as by applying a test function voltage, commonly referred to as a "supervoltage", to one of the external pins of the integrated circuit device. In one example, the supervoltage is 4.5 volts higher than a chip power supply voltage VCC. The integrated circuit memory device includes a circuit that detects the supervoltage and generates a test enable signal, which is applied to test circuits of the device for initiating various test procedures as is known in the art.
FIG. 1, which is labeled "Prior Art", illustrates one known stress test circuit that is used in antifuse test procedures for applying an antifuse stress voltage. During normal operation, the test circuit couples a voltage DVC2E produced at node 120 by a voltage generating circuit 102 to an output node 104 which is connected to a terminal 204 of a conventional antifuse detection circuit, shown in FIG. 2, which is labeled "Prior Art". During normal operation, the antifuse detection circuit is used to indicate whether the antifuse 202 is in an "unblown" or "blown" condition. During a test mode of operation, the test circuit decouples the voltage generating circuit 102 from the output node 104 and couples the output of a tristateable driver 106 to the output node 104 for applying to output node 104 a stress voltage that is derived from the power supply voltage VCC.
Voltage generating circuit 102 includes p-channel transistors 108 and diode-connected, n-channel transistors 110. The test circuit includes a gating circuit 112, embodied as a multiplexer, an enabling circuit 114, including a NOR gate 116 and an inverter 118, and the tri-stateable driver 106. The enabling circuit 114 determines the state of the multiplexer 112 based upon the logic state of test signal SUPERVOLT that is applied to an input of NOR gate 116.
During normal memory device operation, test signal SUPERVOLT is at a logic low level, and the output at node 120 of the voltage generating circuit 102 is coupled to the test circuit output at node 104 through the multiplexer 112. When test signal SUPERVOLT is at a logic high level, the multiplexer 112 is disabled, decoupling the voltage generating circuit 102 from the test circuit output at node 104. Tri-stateable driver 106 has inputs connected to receive the complementary state inputs provided at the output 122 of the NOR gate 116 and the output 124 of inverter 118, respectively, for controlling its operation. Tri-stateable driver 106 also receives an antifuse stress enable signal AF.sub.-- STRESS. When stress enable signal AF.sub.-- STRESS and test signal SUPERVOLT are both at a logic low level, tristateable driver 106 is disabled, providing a high impedance level to the output node 104. When the stress enable signal AF.sub.-- STRESS and test signal SUPERVOLT each become a logic high level, the tri-stateable driver 106 applies a voltage corresponding to the power supply voltage VCC to the output node 104. Output node 104 is connected to a node 204 of the detection circuit which, in turn, is connected to a control terminal of a pass gate, e.g. the gate of an n-channel transistor 206 (FIG. 2) of the antifuse detection circuit.
In FIG. 2, one terminal of the antifuse 202 is connected to the power supply voltage VCC through series-connected p-channel transistors 208, 210 and n-channel transistors 206, 212. The gate terminal of n-channel transistor 212 is coupled to the supervoltage Vccp!, which is typically more positive than the positive supply voltage VCC, as described above. The other terminal of the antifuse is connected to ground through series-connected n-channel transistors 214 and 216. Transistor 206 functions as a pass gate that is controlled by the voltage DVC2E. Transistor 206 limits the voltage at node 207 to antifuse 202 to a level corresponding to DVC2E-V.sub.T, which is less than the power supply voltage VCC, where V.sub.T is the threshold voltage drop of the pass gate transistor 206.
Referring again to FIG. 1, during the antifuse testing procedure, a test signal "SUPERVOLT" disables multiplexer 112, decoupling voltage generating circuit 102 from output node 104. When the antifuse stress enable signal AF.sub.-- STRESS is also provided, tri-stateable driver 106 applies a voltage corresponding to the power supply voltage VCC to the output node 104 for application to the pass gate 206 (FIG. 2). Thus, the voltage that is applied to the control input of pass gate 206 during the antifuse stress test is the power supply voltage VCC. However, stress voltage levels that are different from the levels of power supply voltage VCC (e.g., approximately between 2.5 volts and 8 volts, may be desired during the antifuse stress testing. This is difficult to obtain because the power supply voltage level VCC is established by application of a common external power supply voltage. Moreover, the levels of the supply voltage VCC are not optimum for antifuse stress testing. As a result, a dedicated test is required for antifuse stress testing, i.e. separate from other tests of RAM memory cells. This increases test time, and correspondingly increases manufacturing costs.
For the reasons stated above, and for other reasons stated below which will become apparent to those skilled in the art upon reading and understanding the present specification, there is a need in the art for a test circuit and method for stressing antifuses prior to programming the antifuses, which is independent of the level of the chip supply voltage. There is a further need in the art for such a test circuit and method which eliminates the need for a dedicated test time for antifuse stress testing such that antifuses can be stressed while other circuits on the integated circuit die are undergoing normal testing.